Computer System Architecture - Central Processing Unit
- Option : D
- Explanation : (i) j + 1st instruction uses result of the jth instruction as an operand, then read-after- write (RAW) hazard occurs. It is a part of data dependency.
(ii) Execution of a conditional jump instruction causes a flushing so conditional dependency occurs.
(iii) jth and j + 1st instructions require the ALU at the same time causes write-after-read (WAR) hazard.
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2. Which of the following statements about relative addressing mode is FALSE ?
- Option : D
- Explanation : As relative address are calculated from absolute address, So relative addressing cannot be faster than absolute addressing.
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- Option : D
- Explanation : For any exception, while executing RFE, no exception is alllowed (no interrupts). I t is a priveleged instruction, as soon as exception occurs RFE is called (executed).
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- Option : A
- Explanation : 1 cycle time for p1 = 101/1GH = 1n.s.
Assume p1 takes 5 cycles for a program then p2Â takes 20% more, means, 6 cycles.
p2 Takes 25% less time, means, if p1 takes 5 n.s, then p2 takes 3.75 n.s.
Assume p2 clock frequency is x GHz.
p2 taken 6 cycles, so 6*101/xGH = 3.75, x = 1.6
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- Option : B
- Explanation : There are two functional units each unit get
5 numbers of units to compute on. Suppose
computation starts at time 0.
which means G starts at 0 and F starts at 3rd second since G finishes computing first element at third second.
Time at which F ends computing = 3 + 5 * 5 = 28
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